Table of Contents
ELEN90056 - Electronic Circuit Design
Introduction
There are two types of signals, analogue and digital. The world is full of analogue signals, but it is much easier to work with digital ones. As a result, we sample signals to make them digital, process them and produce new analogue ones. This means that there is a large need for analogue circuit designers. In a mixed chip, with 90% digital and 10% analogue components, 90% of the time will be taken by the analogue components.
Circuit basics
Kirchhoff's Current Law states that the sum of currents into a junction is equal to 0. Kirchhoff's Voltage Law states that the sum of voltages around a loop is equal to 0.
Equivalent circuit models can be used to simplify the modelling of circuits. Thevenin Equivalent Circuits use a voltage source in series with a resistor and can be characterised from the open circuit voltage the current from an applied test voltage. Norton Equivalent Circuits use a current source in parallel with a resistor and can be characterised by the shorted current and the voltage across the terminals.
Semiconductors
Semiconductors exist between conductors and insulators. Undoped (or intrinsic) semiconductors generate electron-hole pairs with electrons with enough energy to cross the band-gap to the conduction band. The band-gap is the energy difference between the top of the valence band and the bottom of the conduction band. If a free electron falls into a hole, it recombines and is no longer a movable carrier. At equilibrium, the rate of free electron generation is equal to the rate of recombination. The higher the temperature, the greater the carrier concentration (and conductivity).
In a semiconductor we can dope in atoms to alter the characteristics of the band-gap. In silicon we can introduce atoms from group 5 of the periodic table, introducing an extra electron when inserted into the crystal lattice. This is n-type doping and increases the conductivity of the crystal, with electrons being the majority carrier. We can also dope with group 3 elements, introducing holes into the crystal due to the extra accepted electron on the atom. This is p-type doping and has holes as the majority carrier.
Electrons and holes can move in drift or diffusion currents. Drift current arises from an electric field, with electrons flowing from positive to negative and holes doing the opposite. The charge carriers bump into atoms as they travel, so the electron velocity is the average carrier velocity. $$J_{drift}=\mu_nE\cdot n\cdot q+\mu_qE\cdot p\cdot q=q(\mu_nn+\mu_pp)E$$ Where $\mu$ is the carrier velocity and it is multiplied by the number of carriers. Diffusion arises from imbalances in concentration of carriers, where the carriers flow from a region of high concentration to one of low. Electrons flow from n-type to p-type and holes from p-type to n-type. $$J_{diffusion}=q\left(D_n\frac{dn}{dx}-D_p\frac{dp}{dx}\right)$$ Where $D$ is the diffusion coefficient and is multiplied by the change in concentration in a direction.
Joining a n-type and p-type material causes diffusion between the regions, which creates an electric field creating a drift current in the opposite direction. Eventually the drift and diffusion currents balance out, resulting in a p-n junction. The region where this occurs has a permanent electric field and is called the depletion region.
Applying an external electric field can change the size of the depletion region. Forward bias is the application of an external field against the depletion region's field. This enables the majority carriers to cross the junction and the greater the bias voltage the greater the numbers of carriers able to cross and thus the current. Reverse bias is the application of the external field with the depletion region's field. This increases the depletion region and stops current from travelling. The current “saturates” at a value corresponding to $I_0$. This is commonly modelled by the ideal diode equation: $$I=I_0(e^{V/V_t}-1)$$ A reverse biased PN junction creates a large electric field that sweeps any injected minority carriers to their majority region. This ability to collect carriers proves essential in the proper operation of a bipolar transistor.
Bipolar Junction Transistors
A BJT consists of three doped regions, forming two junctions. The outer regions are similarly doped and the middle region is oppositely doped. There is a terminal to each region. Where the emitter and collector are n-type, the base is p type, forming a npn transistor. If this is flipped, it is a pnp transistor. The transistor regions are commonly wells placed within each other. The forward active region is when the B-E junction is forward biased and the B-C junction is reverse biased ($V_{BE}>V_t$ and $V_{BC}<V_t$, $V_{CE}>V_{BE}$).
In the transistor there are 2 junctions, and one of the outer semiconductors (emitter) regions will be heavily doped compared to the other regions (base and collector). When the base is biased relative to the emitter, holes are moved from the base, middle region, to the highly doped emitter region, accelerating a lot more electrons from the emitter to the base due to the doping concentration. The electrons then hit the base-collector junction (also biased between collector and emitter) and are accelerated by the junction's electric field as they are the minority carrier in the base region. This is why the current is multiplied: $$I_C=\beta I_B$$ The base has a small E-field, and the drift is negligible as diffusion increases. The field will direct the path of the electrons as they move from the emitter to the collector. The collector current is: $$I_C=\frac{A_EqD_nn_i^2}{N_EW_B}\left(\exp\frac{V_{BE}}{V_T}-1\right)\approx I_S\left(\exp\frac{V_{BE}}{V_T}\right)$$ Where $V_T=\frac{kT}{q}$ is the thermal voltage, where $k$ is the Boltzmann constant, $T$ is the absolute temperature and $q$ is electron charge, as such $V_t\approx 26\text{ mV}$. The transistor functions as a voltage controlled current source when the B-E junction is reverse biased and the B-C junction is forward biased, and the opposite for PNP. For a PNP transistor, the same equations apply, but we need to swap the directions of the currents and voltages. For NPN, $V_{BE}=V_B-V_E$ and for a PNP, $V_{EB}=V_E-V_B$.
We cannot functionally change the gain, $\beta$, by varying $V_{CE}$, as it doesn't affect the number of charges coming from the highly doped region. Attaching a resistor in series with the emitter of the transistor, we are able to convert the current control of the transistor into voltage control and amplification. The emitter current is: $$I_E=I_C\left(1+\frac{1}{\beta}\right)=I_C+I_B$$ We can also find that: $$I_B=\frac{1}{\beta}I_s\exp\frac{V_{BE}}{V_T}$$ $$I_E=\frac{\beta+1}{\beta}I_S\exp\frac{V_{BE}}{V_T}$$ $$\frac{\beta}{\beta+1}=\alpha$$ And the collector emitter voltage with the resistor is: $$V_{CC}=V_{CE}+R_CI_C$$
In biasing, the base-collector junction must be reverse biased, and the base-emitter junction must be forward biased. This is called forward-reverse bias. NPN transistors are written with an arrow going from the base to the emitter, PNP transistors are written with the arrow from emitter to base. In NPN transistors, base and collector currents goes into the transistor with emitter leaving the transistor. In PNP transistors, base and collector currents leave the transistor, with emitter entering. The voltages in the BE junction are flipped in the PNP from the NPN, but still forward biasing the junction. Applying a voltage of $V_{BB}$ across a resistor $R_B$ in series with the base, gives a base current of: $$I_B=\frac{V_{BB}-V_{BE}}{R_B}$$ $$V_{BB}=V_{BE}+R_BI_B$$ Applying a voltage of $V_{CC}$ across the collector in series with a resistor, $R_C$, gives a collector emitter voltage of: $$V_{CE}=V_{CC}-I_CR_C$$ This gives the reverse-biased CB voltage as: $$B_{CB}=V_{CE}-V_{CE}$$
Collector characteristic curves plot $I_C$ against $V_{CE}$, and have two steep regions with a flat region bridging them. The first steep region is the saturation region, the flat is the active and the last steep is the breakdown. The transition from saturation to active is when $V_{CE}\approx V_{BE}\approx 0.7V$. The active region is the properly biased region. The above formula for the collector current, $I_C=I_S\exp(V_{BE}/V_T)$, is only true for the forward active region. When we increase $V_{CE}$, we enter the breakdown region, where the junction starts to breakdown. For smaller $V_{CE}$ values, we enter the saturation region. For an amplifier, we want to operate as close to saturation as possible, without entering saturation. The active region has very little dependence on $V_{CE}$, being almost flat. Changing $V_{BB}$ provides a family of curves, as an increase in $I_B$ provides an increase in $I_C$. The cutoff region is when there is a small leakage current in $I_B$ (due to minority carriers) which is normally ignored. The cutoff region is when the base-emitter and base-collector junctions are reverse biased. At cutoff, $V_{CE}=V_{CC}$. As we decrease $V_{CE}$, the reverse bias across the base-collector junction is reduced, eventually putting the junction in forward bias and leaving the forward active region.
A DC load line can be used to characterise the characteristic curve. It is constructed by varying $V_{BB}$ while holding $V_{CC}$ constant and measuring $I_C$. When $I_C=0$, then $V_{CE}=V_{CC}$ and when $V_{CE}=0$, then $I_C=V_{CC}/R_C$. These intersection point of the DC load line and the $I_C(V_{CE})$ curves provides the operation point of the transistor (saturation voltage and current).
Soft saturation is when $V_{CE}=V_{BE}$ to approximately $V_{CE}=200\text{ mV}$. This means the junction is well below the junction voltage. Deep saturation is when $V_{CE}<200\text{ mV}$ (meaning $V_{BC}\approx 550\text{ mV}$), so the junction is nearly biased. We try to avoid operating BJTs in saturation mode as it can lead to distortions, reductions in speed, amplification, etc. In the deep saturation region, the transistor loses its voltage-controlled current capability and $V_{CE}$ becomes a constant.
BJT models
BJTs can be modelled with the large signal model or the small signal model. The large signal model can be used for arbitrarily large voltage and current changes in the transistor provided the device operates in the active region. If the signal changes the bias points, the transistor operates in large signal domain. The small signal model uses a constant bias but adds a small AC voltage to the biasing, and tests the effect of that on the output. As the small signal is only a small perturbation it is easier to model.
Large signal model
The large signal model, is constructed from a diode between the base and emitter, with current $I_B=\frac{I_S}{\beta}\exp\frac{V_{BE}}{V_T}$. The collector and emitter are connected with a voltage controlled current source with $I_C=I_S\exp\frac{V_{BE}}{V_T}$. While varying $V_{BE}$, $I_C$ exponentially grows. While varying $V_{CE}$, $I_C$ remains approximately constant. The Early effect explains why $I_C$ is not constant as $V_{CE}$ changes. As $V_{CE}$ increases, the depletion region between base and collector increases, decreasing the effective base width leading to an increase to collector current. This is because $I_S$ increases. $$I_S=\frac{A_EqD_nn_i^2}{N_BW_B}$$ This redefines $I_C$ to account for this as: $$I_C=I_S\exp(V_{BE}/V_T)(1+V_{CE}/V_A)$$ Here $V_A$ is the Early voltage, and is used to keep $I_S$ constant. The Early effect can be accounted for by adding in the modification factor to the large signal model.
Small signal model
The transconductance of a transistor, $g_m$, of a transistor is a measure of how well it converts a voltage signal to a current signal. This is one of the most important parameters in integrated circuit design. $$g_m=\frac{dI_C}{dV_{BE}}\approx\frac{d}{dV_{BE}}\left(I_S\exp\frac{V_{BE}}{V_T}\right)=\frac{I_C}{V_T}=\frac{1}{V_T}I_S\exp\frac{V_{BE}}{V_T}$$ $g_m$ can be visualised as the slope if $I_C$ vs $V_{BE}$. A large $I_C$ has a large slope and therefore a large $g_m$. An oscillation of $\Delta V$ in $V_{BE}$ produces an oscillation of $g_m\Delta V$ in $I_C$.
The small signal model comes from altering the voltage difference in every two terminals while fixing the third and analysing the current change in all three terminals. This simplifies non-linear components. We replace all capacitors with short circuits, inductors with open circuits, DC voltage sources with ground and DC current sources with open circuits. We can simplify the base-emitter junction from a diode to a resistor $r_\pi=\beta/g_m$. The collector-emitter junction is still a current source, but is simplified and $V_{CC}$ is grounded. The current source is $I_C=g_mv_\pi$, where $v_\pi$ is the voltage over the BE resistor. This makes $I_C=\beta I_B$.
We can account for the Early effect by adding a parallel resistor between the collector and emitter. This resistor ($r_0$) is in parallel with the current source, providing the dependence on $V_{CE}$. $$r_0=\frac{\Delta V_{CE}}{\Delta I_C}=\frac{V_A}{I_S\exp\frac{V_{BE}}{V_T}}\approx\frac{V_A}{I_C}$$
BJT Impedance
For an amplifier, we want the largest possible input impedance to capture as much of the transmitted signal as possible. We also want the smallest output impedance to transmit as much as possible. To find the input and output impedance, we:
- Set all independent sources to 0
- Apply a test voltage to the two node and measure the current
- Short input for finding output impedance, open output for finding input impedance
As input resistance (base impedance) is dependent on the input current and voltage. $$\frac{v_x}{i_x}=r_\pi=\beta/g_m=\beta V_T/I_C$$ To increase the input impedance, lower the collector current $I_C$ or increase the current gain $\beta$.
The output impedance is infinite without the Early effect, and equal to the Early resistor $r_0$ with the Early effect.
The emitter impedance is dependent on the input current and voltage too: $$r_{out}=\frac{v_x}{i_x}=\frac{1}{g_m+1/r_\pi}\approx\frac{1}{g_m}$$ It is approximately equal to the transconductance, assuming $r_\pi$ is large, meaning $\beta$ is large.
The three master riles of transistor impedances are:
- Looking into the base, the impedance is $r_\pi$ if the emitter is (ac) grounded
- Looking into the collector, the impedance is $r_0$ if the emitter is (ac) grounded (with Early effect) & the impedance is infinity if Early effect is not taken into account
- Looking into the emitter, the impedance is $\frac{1}{g_m}$ if base is (ac) grounded and Early effect is neglected
BJT biasing
In the active region, we have the base-emitter forward biased and the base-collector reverse biased. There are many different biasing schemes, with differing advantages and disadvantages. Many of the disadvantages stem from what $I_C$ is dependent on.
Biasing with a single base resistor causes: $$I_C=\beta\frac{V_{CC}-V_{BE}}{R_B}$$ $$V_{CC}-\beta\frac{V_{CC}-V_{BE}}{R_B}R_C>V_{BE}$$ Assuming a constant $V_{BE}$, we can solve for both $I_B$ and $I_C$ and determine the terminal voltages of the transistor. Its advantage is its simplicity, needing only one resistor. Its main disadvantage is the bias point's sensitivity to $\beta$ variations, making it rarely used.
Using a resistive divider, with the base between the resistors causes: $$V_{BE}=\frac{R_2}{R_1+R_2}V_{CC}$$ $$I_C=I_S\exp\left(\frac{R_2}{R_1+R_2}\frac{V_{CC}}{V_T}\right)$$ Here $I_C$ is relatively independent of $\beta$ if the base current is small. There is an exponential dependence on the resistors, which deviations can make less useful.
We can improve this with emitter degeneration biasing. This inserts a resistor after the emitter. This makes the emitter current approximately: $$I_C\approx I_E=\frac{1}{R_E}\left(V_{CC}\frac{R_2}{R_1+R_2}-V_{BE}\right)$$ The presence of $R_E$ helps to absorb the error in $V_{BE}$, keeping it relatively constant. This is less sensitive to $\beta$ ($I_1\gg I_B$) and $V_{BE}$ variations, making it fairly stable albeit complex.
The self-biasing technique uses a resistor between the collector and base for biasing. This ensures that the collector emitter junction is always reverse biased, so that the transistor is in forward active mode. $$I_C=\frac{V_{CC}-V_{BE}}{R_C+\frac{R_B}{\beta}}$$ If $R_C\gg R_B/\beta$, it provides insensitivity to $\beta$. It is often used in high-speed optical communications due to its insensitivity to $V_{BE}$.
BJT topologies
Common emitter
A common emitter topology has input at the base and output at the collector. A common collector topology has input at the base and output at the emitter. A common base (emitter-follower) topology has the input at the emitter and output at the collector. We cannot put the signal into the collector or take it out of the base.
The common emitter (CE) core begins with a resistor between $V_{CC}$ and the collector, where the output is, and the input is applied to the base. This provides amplification and inversion of the input signal. This provides a gain of $A_v=\frac{V_{out}}{V_{in}}=-g_mR_C$, and $|A_v|=\frac{V_{RC}}{V_T}=\frac{V_{CC}-V_{BE}}{V_T}$. To remain in the forward active region, $|A_V|<\frac{V_{CC}-V_{BE}}{V_T}$. Increasing the gain decreases $V_{out}$ and the voltage headroom, eventually causing clipping if the headroom is negative.
A transistor with a resistor at the emitter and collector has a “degenerate” CE stage. This will decrease the gain of the amplifier but improve other aspects, such as linearity and input impedance. $$A_v=-\frac{g_mR_C}{1+\left(\frac{1}{r_\pi}+g_m\right)R_E}\approx-\frac{R_C}{\frac{1}{g_m}+R_E}\approx-\frac{R_C}{R_E}$$ Using just the transistor and emitter resistor, we can approximate the circuit by its output transconductance: $$G_m=\frac{i_{out}}{v_{in}}=\frac{g_m}{1+(r_\pi^{-1}+g_m)R_E}\approx\frac{g_m}{1+g_mR_E}=\frac{1}{1/g_m+R_E}$$ This is the short-circuit transconductance. If $R_C$ is the collector resistor, the voltage gain is $-G_mR_C$, independent of the transistor transconductance and bias current. The input impedance is $R_{in}=r_\pi+(\beta+1)R_E$ and the output impedance is $R_{out}=R_C$.
When we add a base resistor, the gain becomes: $$A_v\approx\frac{-R_C}{\frac{1}{g_m}+R_E+\frac{R_B}{\beta+1}}$$ The input resistance is: $$R_{in}=R_B+r_\pi+(\beta+1)R_E$$ The output resistance is the same at $R_{out}=R_C$.
With a resistive divider on the base, the gain is: $$A_V=-\frac{R_C}{\frac{1}{g_m}+R_E}$$ $$R_{in}=[r_\pi+(\beta+1)R_C]||R_1||R_2$$ $$R_{out}=R_C$$
Full common emitter
Adding a coupling capacitor in parallel with $R_E$ adds capacitive impedance $X_C=\frac{1}{2\pi fC}$. We assume that the capacitor allows AC but blocks DC. With a resistive divider and the capacitor, the AC gain and resistance is: $$A_v=-g_mR_C$$ $$R_{in}=R_\pi||R_1||R_2$$ $$R_{out}=R_C$$ A coupling capacitor allows us to isolate the bias network from AC input while letting the input pass through. To analyse this, we start with DC analysis with the large signal model to find the small signal parameters which we use to construct the small signal model which we use for analysis.
The complete common emitter stage as a voltage source connected to a resistor ($R_S$) and series capacitor ($C_1$) to a biased (through a voltage divider $R_1,R_2$) base. There is a resistor on the collector ($R_C$) and emitter ($R_E$). The output has a series capacitor ($C_2$) and a parallel load resistor ($R_L$). The gain is: $$A_v=\frac{-R_C||R_L}{\frac{1}{g_m}+R_E+\frac{R_S||R_1||R_2}{\beta+1}}\frac{R_1||R_2}{R_1||R_2+R_S}$$
The Early effect adds a resistor between the collector and emitter, limiting the gain and altering the output resistance. In a small signal model with a resistor on the collector: $$A_v=-g_m(R_C||r_0)$$ $$R_{out}=R_C||r_0$$ The intrinsic gain is independent of the bias current. $$A_v=-g_mr_0$$ Sometimes the Early resistor is drawn in parallel to an ideal BJT.
Degeneration by another transistor
It can be hard to add an emitter resistor, so sometimes a second transistor is used instead. This is a “cascode circuit”, and uses the second transistors' Early resistance to act as a resistor. The output resistance seen is: $$R_{out}=[1+g_{m1}(r_{02}||r_{\pi 1})]r_{01}$$
Common base stage
A common base has the input at the emitter and output at the collector. For a given input $\Delta V$, the output varies by $g_m\Delta VR_C$, while properly biasing the transistor into forward active mode. If $V_{in}$ increases by a small amount, $V_{BE}$ decreases by the same amount, decreasing $I_C$, increasing $V_{out}$. This configuration has a high voltage gain compared to CE, but low current gain. Its input resistance is low compared to CE and output is similarly high to CE. It is used commonly in pre-amplification, moving coil microphones, high-frequency amplification and as a current buffer.
The maximum gain condition is: $$A_v=g_mR_C=\frac{I_C}{V_T}R_C=\frac{V_{CC}-V_{CE}}{VT}=\frac{V_{CC}-V_{BE}}{V_T}$$ The voltage gain is the same as CE, but opposite phase. To maintain active mode operation the voltage drop over $R_C$ must be less than $V_{CC}-V_{BE}$.
Adding a resistor between the source and emitter ($R_S$) alters the gain. This makes the gain: $$A_v=\frac{R_C}{\frac{1}{g_m}+R_S}$$ The source resistor attenuates the signal before it reaches the amplifier, reducing the voltage gain. This is similar to CE emitter degeneration but with the phase reversed. The output impedance without the collector resistor is: $$R_{out1}=[1+g_m(R_E||r_\pi)]r_0+(R_E||r_\pi)\approx r_0+g_mr_0(R_E||r_\pi)$$ The output impedance including the collector resistor is: $$R_{out2}=R_C||R_{out1}$$ The output impedance of the CB stage is equal to $R_C$ in parallel with the impedance looking down the collector. The output impedances of the CE, CB stages are the same if both circuits are under the same condition. This is due to the grounding of the input port when calculating the output impedance, making them the same circuit.
The input impedance at the emitter with CB core is: $$R_{in}\approx\frac{1}{g_m}$$ With a base resistor, this becomes: $$R_{in}\approx\frac{1}{g_m}+\frac{R_B}{\beta+1}$$ With an emitter resistor: $$R_{in}\approx\frac{1}{g_m}||R_E$$ The input impedance is generally low and can be matched to transmission line impedances of $\sim 50\Omega$.
Common collector stage
The Common Collector (Emitter Follower) has the input applied to the base and the output is from the emitter. Increasing $V_{in}$ increases $V_{BE}$, increasing $I_C$ and $I_E$, increasing $V_{RE}$ and $V_{out}$. The change in $V_{out}$ is always less than or equal to the change in $V_{in}$. The input resistance is: $$R_{in}=r_\pi+(1+\beta)R_E$$ The output resistance is: $$R_{out}=\frac{1}{g_m}||R_E$$ The gain is: $$\frac{v_{out}}{v_{in}}=\frac{1}{1+\frac{r_\pi}{\beta+1}\frac{1}{R_E}}\approx\frac{R_E}{R_E+\frac{1}{g_m}}$$ The EF or CC configuration acts as a buffer, presenting a high impedance input with a low impedance output. With a source resistor but no Early effect, the output impedance is: $$R_{out}=\left(\frac{R_S}{\beta+1}+\frac{1}{g_m}\right)||R_E$$ With the Early effect, the output resistance is: $$R_{out}=\left(\frac{R_S}{\beta+1}+\frac{1}{g_m}\right)||R_E||r_0$$ If inserted as a voltage buffer, the emitter follower lowers the output impedance by a factor of $\beta+1$.
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)
For most analogue uses, BJTs are more useful, but MOSFETs are more useful for digital work. The Metal Oxide Semiconductor (MOS) forms a capacitor. $$C=\frac{\varepsilon A}{d}=\frac{\varepsilon_0kA}{d}$$ $k$ is the relative permittivity of the material. We replace one of the plates of the capacitor with the semiconductor material. The dielectric thickness is less than 2 nm. There are n-type (NMOS) and p-type (PMOS) type transistors. The MOSFET terminals are Source, Gate and Drain. The source and drain are identical, unlike the BJT. On the symbol, there is an arrow on the source, pointing out is NMOS and in is PMOS, like a BJT. The channel length is the distance between the source and drain. CMOS technology combines NMOS and PMOS transistors onto the same substrate. This is done by creating a well of the complimentary type for the transistor. There can also be a 4th terminal for the body, controlling the substrate voltage.
As voltage is applied to the gate, positive holes are repelled, leaving negative ions. Then electrons are pulled towards the gate, creating a channel (inversion layer). The gate potential at which the channel begins is the threshold voltage ($V_{TH}\approx300\text{ to }500mV$) and is similar to switching $V_{BE}$ on a BJT.
Once the threshold voltage is reached, current can begin to flow from the drain to source. There is a linear (ohmic) region where the transistor is operating in Triode mode, where $V_{DS}$ affects $I_D$. To the right is the saturation mode, where $I_D$ is independent of $V_{DS}$. $I_D$ in saturation is dependent on $V_{GS}$. Saturation occurs when the channel is slightly short of the drain, due to $V_{GD}<V_{GS}$ causing the current to maximise. In the linear region, we can create a voltage dependent resistor, as the resistance is dependent on the gate voltage, allowing different amounts of $I_D$ for the same $V_D$. We can use this to make a voltage controlled attenuator, allowing for a controllable gain in an op amp.
Varying the channel length (distance between source and drain) varies the relationship between the gate voltage and the drain current, due to changing the capacitance. A shorter length means a steeper curve, with a greater effect on the current of an increased voltage. It also affects the $I_D$ $V_D$ relationship, with a shorter channel having a greater dependence of $I_D$ on $V_D$. The oxide thickness affects the $I_D$ $V_G$ relationship similarly to the channel length, due to changing the capacitance. It has the same effect on the $I_D$ $V_D$ relationship too. There is a slight dependence on the threshold voltage with the oxide thickness too. The width is the overall width of the transistor. Increasing the width increases the dependence of $I_D$ on $V_G$ and $V_D$. This can be thought of as putting transistors in parallel. As the gate width increases, the current increases due to a decrease in resistance. There is also a increase in capacitance, affecting the speed of the circuit.
As we move from the source to the drain, the channel becomes thinner and thinner. This is because the voltage difference to the gate at the drain is less than at the source. This is channel pinch off, and when the channel is pinched off we transition to the saturation region from the triode ($V_G-V_D=V_{TH}$). Pinch off is when the channel extends just to the drain, ending as soon as the channel reaches the drain. When the channel ends before the drain, there is an electric field around the drain, saturation. This allows the modulation of the channel length and is analogous to the Early effect.
The capacitance is: $$C=C_{ox}W$$ Where $C_{ox}$ is the capacitance per width and $W$ is the width. The charge on the gate is: $$Q=CV$$ Where $V$ is the voltage difference between the gate and channel $V_{GS}-V_{TH}$. The channel charge density is: $$Q=WC_{ox}(V_{GS}-V_{TH})$$ Due to the pinch off, the voltage and thus charge density varies from source to drain: $$Q(x)=QC_{ox}[V_{GS}-V(x)-V_{TH}]$$ The drain current is: $$I_D=WC_{ox}[V_{GS}-V(x)-V_{TH}]\mu_n\frac{dV(x)}{dx}$$ For linear charge density, this current becomes: $$I_D=\frac{\mu_nC_{ox}W}{L}\left[(V_{GS}-V_{TH})V_{DS}-\frac{1}{2}V_{DS}^2\right]$$ In the saturation region we can set $V_{DS}=V_{GS}-V_{TH}$, becoming: $$I_{D,max}=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2$$
Large signal model
In the triode region, $I_D$ $V_{DS}$ curve intersects the origin and follows a parabola with a peak at $\left(V_{GS}-V_{TH},\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2\right)$. For different $V_{GS}-V_{TH}$, the peak height and location varies, being pushed to the top right as it increases. Near the origin, this change is approximately linear. We can approximate this to: $$I_D\approx\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})V_{DS}$$ This gives a resistance of: $$R_{on}=\frac{1}{\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})}$$ At small $V_{DS}$, the transistor can be viewed as a resistor, with resistance depending on the gate voltage. This can be useful for the application of an electronic switch.
In the saturation region, the gate voltage is less than the drain voltage, unlike the triode region. Without channel length modulation, $I_D=I_{D,max}$, however increasing $V_{DS}$ decreases the length of the channel due to the channel having been pinched off. We account for this change in channel length by adding in a term, similar to the early effect. $$I_{D\lambda}=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2(1+\lambda V_{DS})$$ Here we use $\lambda$ to account for the channel length modulation. $$\lambda V_{DS}=\frac{\Delta L}{L}$$ For a large channel, there is a small effect from this modulation. As the channel length can be controlled, this can be factored into the design, unlike with BJTs for which the width cannot be easily adjusted. A MOSFET is smaller than real resistors and can pass a large current through a large resistance without a large voltage drop.
Both of these currents can be used to construct a large signal model, with an open circuit between the gate and source. In the deep triode region (assumed to be ohmic), we can replace the voltage dependent current source between the drain and source with $R_{on}$.
For PMOS transistors, the arrow points into the transistor, and the arrow is always on the source side. Current is assumed to flow from source to drain. Cut off is when $V_{SG}<|V_T|$, the triode region is when $V_{SG}>|V_T|,V_{SD}\leq V_{SG}-|V_T|$ and saturation is when $V_{SG}>|V_T|,V_{SD}>V_{SG}-|V_T|$. Like in BJTs, a PMOS behaves like a NMOS but with all polarities reversed.
Small signal model
A MOSFET has transconductance relating the change in drain current to the change in gate voltage measured in the saturation region. $$g_m=\frac{\partial I_D}{\partial V_{GS}}=\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})=\sqrt{2\mu_nC_{ox}\frac{W}{L}I_D}=\frac{2I_D}{V_{GS}-V_{TH}}$$ Without channel length modulation, we get a open circuit between the gate and source, with a current source between the drain and source of $g_mV_{GS}$. Adding in channel length modulation adds a resistor in parallel to the current source of: $$r_0=\frac{1}{\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2\lambda}\approx\frac{1}{\lambda I_D}$$ The small signal model can be used when the bias point doesn't change. The input impedance is infinite, although the oxide layer can have some low leakage current which is usually negligible. The output impedance is $r_0$.
MOSFETs as resistors
MOSFETs can be used as resistors, and are advantageous due to their small size and changeable resistance. When configured with a drain and source resistor, the output gain from the drain is: $$A_v=\frac{-R_D}{\frac{1}{g_m}+R_S}$$ We can replace the source resistor with a MOSFET in a diode configuration (gate connected to drain) and the drain resistor with a secondary input. This gives the source resistance as $\frac{1}{g_{m3}}||r_{03}$ and the drain resistance as $r_{02}$. The gain then becomes: $$A_v=-\frac{r_{02}}{\frac{1}{g_{m2}+\frac{1}{g_{m3}}||r_{03}}}$$
The diode configuration connects the gate to the drain. Here the input voltage is equal to the drain-source voltage. The input current is: $$i_x=g_{m}v_1+v_1/r_0=v_x(g_m+1/r_0)$$ $$v_x/i_x=(1/g_m)||r_0$$ This is the same for both NMOS and PMOS devices. Provided $V_{GS}$ is large enough, this configuration will always be in saturation.
Common source configuration
A common source stage adds a resistor to the source of the transistor. The output resistance of this configuration is: $$R_{out}=(1+g_mr_0)R_S+r_0\approx g_mr_0R_s+r_0$$ This is fairly similar to the BJT, lacking $r_{\pi}$ as the input resistance is assumed infinite in the MOSFET case. Similar to BJT, degeneration boosts the output impedance. Substituting the source resistor with a diode configured MOSFET gives: $$R_{out}=r_{01}\left(1+g_{m_1}\frac{1}{g_{m_2}||r_{02}}\right)+\frac{1}{g_{m2}}||r_{02}\approx r_{01}\left(1+g_{m1}\frac{1}{g_{m2}}\right)+\frac{1}{g_{m2}}$$ Using multiple MOSFETs as drain resistors adds the resistance in parallel. This shows the MOSFET being a versatile resistor when connected to the drain or a separate voltage source.
For CE AND CS staging with a diode connected load, the gain for BJT is: $$A_v=-g_{m1}(r_2||1/g_{m2})\approx-1$$ Where the diodes are the same as $r_2>>\frac{1}{g_{m2}}$. In MOSFETs common source, the gain is: $$A_v=-g_{m1}\frac{1}{g_{m2}}=-\sqrt{\frac{(W/L)_1}{(W/L)_2}}$$ With channel length modulation, the gain becomes: $$A_v=-g_{m1}\left(\frac{1}{g_{m2}}||r_{02}||R_{01}\right)$$
Common gate
A common source is similar to a BJT common emitter. A common gate is similar to a BJT common base. A common drain is similar to a BJT common collector.
A common gate stage has a resistor on the drain and the input applied to the source. $$I_D=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2$$ While in saturation, increasing $V_{in}$ decreases $V_{GS}$, decreasing $I_D$ and increasing $V_{out}$. The gain is: $$A_v=g_mR_D$$ This gain is similar to the common base, both producing positive gain and both are useful in high frequency applications due to its low input impedance.
The input impedance is: $$i_x=-g_mv_x$$ $$R_{in}=\frac{1}{g_m}$$ The output impedance is: $$R_{out}=R_D$$ This is similar to the common base stage.
Adding a resistor to the source causes the gain to become: $$A_v=\frac{R_D}{\frac{1}{g_m}+R_S}$$ When a source resistance is presence, the voltage gain is equal to the CS with degeneration, but positive.
Adding a voltage divider to the gate ($R_1,R_2$) and a resistor to ground at the source ($R_3$) causes the gain to become: $$A_v=\frac{R_3||(1/g_m)}{R_3||(1/g_m)+R_S}g_mR_D$$ Here $R_1$ and $R_2$ provide a bias voltage and $R_3$ provides a path for the DC bias current of the transistor to flow to ground. The voltage divider does not affect the small signal behaviour at low frequencies.
Source follower
The source follower is similar to the BJT emitter follower. There is a resistor connected to the emitter, where the output is taken. The input is provided to the gate. The gain is: $$A_v=\frac{g_m(r_0||R_L)}{1+g_m(r_0||R_L)}<1$$ The input impedance is infinite and the output impedance is: $R_{out}=\frac{1}{g_m}||r_0||R_L$. The output impedance is relatively low with a high input impedance, making it a good candidate as a buffer.
Common biasing has a resistor between $V_{DD}$ and the gate $R_G$ and capacitors between the input and output. $$I_D=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_DD-I_DR_S-V_{TH})^2$$
Cascode configurations
Cascode current sources
A resistive current source has a linear relationship between current and voltage. An ideal current source has a constant relationship between current and voltage, effectively immune to resistance. For a MOSFET, the saturation region functions effectively as an ideal current source, with the current independent of the voltage provided $V_{DS}$ doesn't fall into the triode region. A NMOS draws current from a point to ground, sinking the current. A PMOS draws current from $V_{DD}$ to a point, sourcing current. In both, the rest of the circuit must be connected to the drain for the transistor to act as a current source. The same is true for BJTs. This is because we need a constant $V_{BE}$ and a large $R_{out}$. Using a transistor as a current source allows us to maximise the voltage gain, realising the same gain at a lower voltage, with a smaller voltage drop. Additionally, transistors are smaller than resistors, saving space on an IC.
The Early effect affects the current source, by adding in a resistance, but this can be reduced by adding emitter degeneration. We can replace the emitter resistor with a cascode transistor. $$R_{out}=[1+g_m(R_E||r_\pi)]r_0+R_E||r_\pi=[1+g_{m1}(r_{02}||r_{\pi1})]r_{01}+r_{02}||r_{\pi1}\approx g_{m1}r_{01}(r_{02}||r_{\pi1})$$ Adding the emitter resistor massively increases the output impedance, but does so with diminishing terms. The maximum output impedance is: $$R_{out,max}=\beta_1r_{01}$$ The maximum output is bounded by $r_{\pi}$ from the first transistor. The first transistor is the one closest to the rest of the circuit.
For a CMOS cascode stage, the output resistance is: $$R_{out}=(1+g_mR_s)r_0+R_S=(1+g_{m1}r_{02})r_{01}+r_{02}=r_{02}(g_{m1}r_{01}+1)\approx g_{m1}r_{01}r_{02}$$ This is the same as BJT, but with out $r_\pi$. The output impedance is proportional to the intrinsic gain of the cascode device. Unlike the BJT cascode, the output impedance is not limited by $\beta$.
Parasitic resistance is unwanted resistance due to a manufacturing fault and inherent physical properties. It effectively adds a resistor in parallel to the faulty component.
A false cascode is a circuit that resembles a cascode circuit, but fails to boost the output resistance. This can be done by using a pnp in place of an npn transistor.
Cascode amplifiers
The gain of a common emitter stage is: $$A_v=-g_m(R_D||r_0)$$ $R_D$ can be substituted for an ideal current source, making the gain dependent only on $r_0$, which we can increase with a cascode. This can be done by adding a transistor between the input transistor and the output. The output impedance is: $$R_{out}=[1+g_{m2}(r_{01}||r_{\pi2})]r_{02}+R_{01}||r_{\pi2}\approx g_{m2}r_{02}(r_{01}||r_{\pi2})$$ The gain then becomes: $$A_v=-g_{m1}g_{m2}r_{02}(r_{01}||r_{\pi2})$$ The gain is increased by increasing the output impedance. This could be thought of as a CE stage in series with a CB stage. The same can be done with MOSFETs, removing the $r_{\pi}$ terms. $$A_{v}=-G_mR_{out}\approx-g_m[)1+g_{m2}r_{02}r_{01}+r_{02}]\approx-g_{m1}r_{01}g_{m2}r_{02}$$
We can replace the ideal current source with a transistor acting as a current source. The current source transistor needs to be of the opposite type to the amplifier, such that the collector is visible to the output. This then makes the gain: $$A_v\approx g_{m1}g_{m2}r_{02}(r_{01}||r_{\pi2})||r_{03}$$ We can increase $r_{03}$ by making it a cascode stage. The cascode then makes the whole system output impedance: $$R_{out}\approx g_{m3}r_{03}(r_{04}||r_{\pi3})||g_{m2}r_{02}(r_{01}||r_{\pi2})$$ The first term is from the current source and the second is from the amplifier. For the MOSFET version, we send $r_{\pi}\to\infty$.
Short circuit transconductance
The short circuit transconductance method is based on: $$A_v=-G_mR_{out}$$ To find the gain, we need the output impedance and $G_m$. We ground the output, and treat the circuit as a whole. In some cases, $G_m$ will be equal to the transconductance of an individual transistor in the circuit. $G_m$ can be found by grounding the output to the circuit and finding the current going into the output compared to the input voltage. The output resistance can be found by grounding the input and applying a small test voltage to the output.
Current mirrors
Despite biasing, there are many externally dependent variables, e.g. $V_t$, $V_{CC}$, etc. A band gap reference circuit creates a temperature and supply independent bias source. The stable bias produces the “golden current”. The typical band gap circuit is complex and prohibits its use multiple times for a large IC. Copying the golden current without duplicating the band gap circuitry can be done with current mirrors.
A current mirror ideally duplicates its input current. This can be done by creating a specific $V_{BE}$ and using it to create a copy of the current. The voltage can be created with a diode configured BJT, which creates the base-emitter voltage which enables the current to flow through the transistor. No current is assumed to flow into the base of the transistor. This can be directly connected to the base of another transistor. As both transistors have the same $V_{BE}$, their $I_C$ is ideally the same. $$I_{copy}=\frac{I_{S1}}{I_{S,ref}}R_{REF}$$ Provided the transistors are very similar, the copied current is similar to the reference. This can be duplicated by connecting more transistors in parallel.
Connecting the collectors of some transistors allows us to multiply the reference current by the number of transistors. This effectively increases the area of the transistor. Taking the reference current and inputting it into multiple reference transistors allows us to fractionally scale the reference current.
The base current results in the difference between $I_{REF}$ and $I_{copy}$. This is because $I_{REF}$ splits and only $I_{C,REF}$ is copied. Because the $I_{B,REF}$ needs to supply the base current for all the BJTs, the more copies we make, the greater the error. This doesn't exist for MOSFETS as they have no gate current. We have a current of $\frac{I_{copy}}{\beta}$ going toward the copying transistors and a current of $\frac{I_{copy}}{n\beta}$ going toward the reference transistor. From this, we can find the $I_{REF}$: $$I_{REF}=I_{C,REF}+\frac{I_{copy}}{\beta}\frac{1}{n}+\frac{I_{copy}}{\beta}$$ As $I_{copy}=nI_{C,REF}$, we can find the copied current: $$I_{copy}=\frac{n_{I_{REF}}}{1+\frac{1}{\beta}(n+1)}$$ As $n$ increases, so does the copy error. Likewise, small values of $\beta$ lead to a larger error in $I_{copy}$. For large $\beta$ and moderate $n$, $I_{copy}\approx I_{REF}$.
We can improve the current mirror accuracy by adding a transistor between the reference and base currents, such that the emitter is connected to the base of the mirroring transistors. This further reduces the draw on the base current by a factor of $\beta$. The current into the base of this transistor becomes: $$I_{B,F}=\frac{I_{copy}}{\beta^2}\left(1+\frac{1}{n}\right)$$ The copied current then becomes: $$I_{copy}=\frac{nI_{REF}}{1+\frac{1}{\beta^2}(n+1)}$$
A reference current cannot run to ground, due to its circuitry, so to make a PNP mirror, we must first use a NPN mirror and use the copied current for the PNP mirror. This does introduce some error, but it is small. MOS transistors can be used as current mirrors, and follow the same rules as BJTs. For MOSFETs, the width to length ratio is analogous to the area of the BJT, allowing us to alter the ratio of reference to copied currents.
Differential amplifiers
Large signal analysis
Rectification is the process of converting AC to DC. This process results in an approximation of a flat line, with the variation from that line being ripple. This ripple is an AC component riding on the rectified DC. Sophisticated rectifiers can reduce ripple, but not eliminate it. When used for an amplifier, the ripple can add to the signal and produce noise after amplification.
Taking the difference between two sources with the same ripple produces an output without ripple, removing it in the process. Using two common emitter transistors, connected to the same bias and $V_{CC}$ and taking the output as the difference between the stage with the input and the stage without, we can remove the source ripple and get the resultant gained signal. The duplicate stage without the input remains idle, wasting current. If we connect the input to both transistors we get no output as both stages provide the same amplification. If instead we apply a $180^\circ$ phase shifted input to the second stage, we get double the gain as the resultant signal. The phase shift can be achieved with a centre tap transformer and can be biased to produce the differential signals. A single ended amplifier is one that takes a single input. A differential amplifier is one that takes two inputs and compares two outputs. Connecting the emitters together and to a constant tail current source cause the transistors to operate as a differential pair.
In a common mode differential pair where the biasing resistors are the same, the output voltage is: $$V_{X}=V_{Y}=V_{CC}-R_C\frac{I_{EE}}{2}$$ This produces a zero differential output. To avoid saturation, the collector voltages must not fall below the base voltages: $$V_{CC}-R_C\frac{I_{EE}}{2}\geq V_{CM}$$ Provided the transistors remain forward biased, the bias voltage can be changed without affecting the output.
For a large differential input differential pair, the emitter voltage is determined by the higher biased transistor. This results in the other transistor being off and all the current flowing through the higher biased transistor. $$V_X=V_{CC}-R_CI_{EE}$$ $$V_Y=V_{CC}$$ Here $Q_1$ hogs all of the tail current, turning $Q_2$ off. As the difference between the two inputs depart from 0, the differential pair steers the tail current from one transistor to the other. The share of the currents is given by: $$I_{C1}=\frac{I_{EE}}{1+\exp{\frac{V_{in2}-V_{in1}}{V_T}}}$$ $$I_{C1}=\frac{I_{EE}}{1+\exp{\frac{V_{in1}-V_{in2}}{V_T}}}$$ As $V_{in1}-V_{in2}\to\infty$, being the first input increases above the second, all the current flows through $I_{C1}$ and non flows through $I_{C2}$. As $I_{C1}+I_{C2}=I_{EE}$, we can find: $$I_{C1}=\frac{I_{EE}\exp\frac{V_{in1}-V_{in2}}{V_T}}{1+\exp\frac{V_{in1}-V_{in2}}{V_T}}$$ We can then use this to find $V_{out1}$ and $V_{out2}$: $$V_{out1}=V_{CC}-R_{C1}I_{C1}=V_{CC}-\frac{R_{C1}I_{EE}\exp\frac{V_{in1}-V_{in2}}{V_T}}{1+\exp\frac{V_{in1}-V_{in2}}{V_T}}$$ $$V_{out2}=V_{CC}-R_C\frac{I_{EE}}{1+\exp\frac{V_{in1}-V_{in2}}{V_T}}$$ The difference between them then becomes: $$V_{out1}-V_{out2}=-R_C(I_{C1}-I_{C2})=-R_CI_{EE}\tanh\frac{V_{in1}-V_{in2}}{2V_T}$$
The nonlinear region is where the current flows through only one transistor. The small signal region is for input differences of less than $10mV$. The linear region is where both transistors still flow some current and the input difference is less than $4V_T\approx 104mV$.
Virtual ground
A virtual ground is a point in a circuit where the voltage is 0. This can be between equally and oppositely biased resistors forming a DC virtual ground. If we then add opposite AC signals to each input, the virtual ground remains. If the DC biases are different but the AC signals are equal and opposite, then there is only an AC virtual ground.
Small signal analysis
For a differential pair where there is a sudden, small, equal and opposite change in the inputs, the currents rise and fall by the same amounts. $$I_{C1}=\frac{I_{EE}}{2}+\Delta I$$ $$I_{C2}=\frac{I_{EE}}{2}-\Delta I$$ For small changes at the inputs, the $g_m$ are the same and as the change in currents are the same, the common emitter node can be viewed as an AC ground.
The transconductance is $\Delta I_C/\Delta V=g_m$. The differential gain becomes: $$A_v=\frac{\text{Change in Differential Output}}{\text{Change in Differential Input}}=\frac{-2g_m\Delta VR_C}{2\Delta V}=-g_mR_C$$ This gain is the same as one single-ended transistor. The two transistors must exhibit approximately equal transconductances and the same condition required for the common node to appear as a virtual ground. This grounding in the middle allows us to treat the differential pair as two CE “half circuits”, with total gain equal to one half circuit's single-ended gain. For a perfectly symmetrical circuit, the early effect can be calculated for one of the halves and contributes equally to the other and thus the overall circuit. $$A_v=-g_mr_0$$
Where there is a resistor connecting the emitters of the differential pair, the resistor can be halved and grounded when building the half-circuit. This is due to the virtual ground formed and the resistor affecting both halves. $$A_v=\frac{-R_C}{\frac{R_E}{2}+\frac{1}{g_m}}$$
Where there is a pair of transistors with a common base connected to the collector of the differential pair, with a resistor connecting the each new emitter to the common base, a virtual ground is formed at the common base. This causes the gain to become: $$A_v=-g_{m1}(r_{01}||r_{03}||R_{1})$$ If instead the transistors are externally biased and the resistors are connected to each other, the gain stays the same.
For a large signal input, the output can become clipped, becoming linear and flat for part of the signal as the gain cannot be applied. This is when there is no more current available to contribute to the gain. An input difference of $4V_T$ is sufficient to turn one side of the bipolar pair nearly off. This can be used to remove some noise occurring at the peaks of an input signal.
In a MOS differential pair, there exists a finite differential input voltage to completely switch the current from one transistor to the other, whereas in a bipolar pair that voltage is infinite. For a BJT, the maximum differential input voltage is $|V_{in1}-V_{in2}|_{\max}=4V_T$ (larger than $10mV$ for small signal applications). For a MOS, the maximum differential input voltage is $|V_{in1}-V_{in2}|_\max=\sqrt{2}(V_{GS}-V_{TH})_{equil}$. In MOS, an input difference of the following is considered small. $$|V_{in1}-V_{in2}|<<\frac{4I_{SS}}{\mu_nC_{ox}\frac{W}{L}}$$
Common Mode Rejection Ratio (CMRR)
The common mode response for a differential pair is when the inputs are equal, and the output does not vary. This assumes perfect symmetry and ideal current sources. If the same noise is applied to the common mode, the output is isolated from the noise, with the noise going to the common emitter. The noise is absorbed by the infinite impedance current source. As no infinite impedance source exists, we can model the emitter resistor with $R_{EE}$, giving the common-mode gain as: $$A_v=-\frac{R_C}{2R_EE+\frac{1}{g_m}}$$ A change to the input CM voltage causes the currents in the transistors to change, leading to a change in $V_{out1}$ and $V_{out2}$. This passes some of the noise through to $V_{out1}$ and $V_{out2}$, however as $V_{out}$ is the difference, the noise is still cancelled. This is similar to the removal of ripple voltage. If the $R_C$ differ from each other, then the output voltages are not symmetrical, so any noise is passed through to the output.
In an asymmetrical circuit, a fluctuation in the common mode is interpreted as a differential mode input. This is a common mode (CM) to differential mode (cm) conversion, $A_{CM-DM}$. For a MOSFET differential pair, the common mode gain is: $$A_{CM-DM}=\frac{\Delta R_D}{1/g_m+2R_{SS}}\approx\frac{\Delta R_D}{2R_{SS}}$$ Ideally, this should be 0, which is achieved when $R_{SS}\to\infty$ or $\Delta R_D\to 0$. If a finite tail impedance and asymmetry are both present, then the differential output will contain a portion of input common-mode signal.
The Common Mode Rejection Ratio (CMRR) is the ratio of the differential mode gain to the common mode gain: $$CMRR_{DM}=\frac{A_{DM}}{A_{CM-DM}}$$ This is the ratio of wanted input signal amplification to unwanted common mode noise amplification. Ideally the CMRR is infinite.
Single ended conversion
Many components take two signals as input and produce only a single output. It can be useful to only have a single output. One way of converting is to take the only one of the outputs, say $V_{out2}$ and use that as the output, but this is not great, as it doesn't utilise the differential nature of the circuit and is still sensitive to noise. This also results in losing half the signal.
Adding a current mirror in place of the collector resistors creates an active load which puts the current difference between the sides into the output line. $$I_3=I_1-I_2=\frac{I_{EE}}{2}+\Delta I-\left(\frac{I_{EE}}{2}-\Delta I\right)=2\Delta I$$ $$V_{out}=2\Delta I R_L$$ Usually a capacitor will be used to decouple the DC component from the output. Adding in the current mirror removes the symmetry, requiring small-signal analysis to find the gain The common emitter is no longer a virtual ground, but the circuit can still be viewed as a differential pair. The gain is: $$A_v=\frac{v_{out}}{v_{in1}-v_{in2}}=g_{mN}(r_{0N}||r_{0P})$$ Where $g_{mN}$ is the differential pair transistor transconductance, $r_{0N}$ is the differential pair Early resistance and $r_{0P}$ is the current mirror Early resistance.
Frequency responses
Generally, the gain of an amplifier is inversely related to the frequency of operation. $$Z_c=\frac{1}{2\pi fC}$$ Here, we can see that the amplifier's capacitance is limiting. The output of an amplifier has a capacitive load connecting the output to ground, which we can use to model the gain. $$A_v=-g_m\left(R_D||\frac{1}{C_Ls}\right)=\frac{-g_mR_D}{R_DC_Lj\omega+1}$$
The transfer function is the gain of the system, being the relationship between the input and output $|V_{out}/V_{in}|$. $$H(j\omega)=A_0\frac{\left(1+\frac{j\omega}{\omega_{z1}}\right)\left(1+\frac{j\omega}{\omega_{z2}}\right)...}{\left(1+\frac{j\omega}{\omega_{p1}}\right)\left(1+\frac{j\omega}{\omega_{p2}}\right)...}$$ Where $A_0$ is the low-frequency gain, $\omega_z$ are the “zero” frequencies and $\omega_p$ are the “pole” frequencies. We can note that $H(j\omega)\to A_0$ as $s\to 0$, where $s=j\omega=j2\pi f$. We can use this to find the pole of the previous gain, $\omega=\frac{1}{R_DC_L}$, giving the absolute value of the gain as $\left|\frac{V_{out}}{V_{in}}\right|=\frac{g_mR_D}{\sqrt{2}}$. This is about $70\%$ of the low frequency gain, and occurs at the $-3dB$ frequency. We can show the gain on a Bode plot, which will be roughly flat initially and fall off at 20dB/decade after the 3dB frequency.
Miller's Theorem
Miller's theorem accounts for a floating capacitor connecting the drain and gate of the transistor. The theorem replaces the floating capacitor into two equivalent grounded capacitors. For the first node (gate/input), we have: $$Z_1=\frac{Z_F}{1-A_v}$$ For the second node (drain/output), we have: $$Z_2=\frac{Z_F}{1-1/A_v}$$ Where $A_v$ is the gain from the gate to drain.
The input capacitance is: $$C_{in}=C_F(1+A_0)$$ The output capacitance is: $$C_{out}=C_F(1+1/A_0)\approx C_F$$ Where $A_0=-A_v$. Miller multiplication refers to the multiplicative increase in input capacitance.
Miller's theorem is only true if we use $A_v$ and $Z_F$ at the same frequency of interest. The Miller approximation ignores the effect of the capacitor on the gain, effectively using the low frequency gain for everything, even the high frequency poles. This approximation is close to real results.
Intrinsic capacitance
In MOS transistors, there exists oxide capacitance from gate to channel, junction capacitances from source/drain to substrate, and overlap capacitance from gate to source/drain. These capacitances will start to effect the transistor at high frequency, as they will start acting like shorts. Some of the capacitances are from multiple regions around the MOSFET.
With these capacitances, it is possible to define a quantity representing the ultimate speed of the transistor. The transit frequency $f_T$ is defined as the frequency where the current gain from input to output drops to 1. Normally, it is the capacitance between the base and emitter ($C_\pi$) that is the limiting factor in BJTs. We can find the transit frequency to be: $$2\pi f_T\approx\frac{g_m}{C_\pi}$$ For MOSFETS, we can find the transit frequency as: $$2\pi f_T\approx\frac{g_m}{C_{GS}}$$
Feedback
Two types of feedback exist, positive and negative.
- Positive feedback systems add a feedback signal to the input signal and are used in some specific devices, e.g. oscillators.
- Negative feedback systems involve subtracting a feedback signal from the input signal and are widely used for improving stability.
Negative feedback
For a system with a feed forward gain if $A_1$ and a feedback gain of $K$, the closed loop transfer function is: $$\frac{Y}{X}=\frac{A_1}{1+KA_1}$$ The negative feedback reduces the gain by a factor of $\frac{1}{1+KA_1}$.
The feedback error $E$ is the modified signal applied to the feed forward system. $$E=X-X_F=\frac{X}{1+A_1K}$$ As $A_1K$ increases, the error between the input and feedback signal decreases, meaning the feedback signal is a good replica of the input. This condition is favourable for gain desensitisation/stability. In increasing the gain ($KA_1\to\infty$), we can find that $X\approx X_F$. We can use this to find the gain, and find that it is independent of $A_1$. This separates the closed loop gain from the open loop gain.
The main advantage of negative feedback is gain desensitisation, which increases the stability of the system. It can also serve to modify the input and output impedances. The lower gain enforced by the feedback means the gain remains constant over a larger bandwidth. Keeping the error small helps to keep the system acting linearly.
The loop gain is found by:
- Breaking the circuit at an arbitrary location and setting the input to ground
- Connecting a test voltage source such that there is clockwise current
- Finding the gain at the other node compared to the test input ($-\frac{V_N}{V_{test}}$)
This is $KA_1$.