Differences

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--- notes:elen90056 [2021/09/03 00:26] – created joeleg
+++ notes:elen90056 [2023/05/30 22:32] (current) – external edit 127.0.0.1
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 Kirchhoff's Current Law states that the sum of currents into a junction is equal to 0. Kirchhoff's Voltage Law states that the sum of voltages around a loop is equal to 0.
-Equivalent circuit models can be used to simplify the modelling of cirtcuits. Thevenin Equivalent Circuits use a voltage source in series with a resistor and can be characterised from the open circuit voltage the current from an applied test voltage. Norton Equivalent Circuits use a current source in parallel with a resistor and can be characterised by the shorted current and the voltage across the terminals.
+Equivalent circuit models can be used to simplify the modelling of circuits. Thevenin Equivalent Circuits use a voltage source in series with a resistor and can be characterised from the open circuit voltage the current from an applied test voltage. Norton Equivalent Circuits use a current source in parallel with a resistor and can be characterised by the shorted current and the voltage across the terminals.
 ====== Semiconductors ======
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 The maximum gain condition is: $$A_v=g_mR_C=\frac{I_C}{V_T}R_C=\frac{V_{CC}-V_{CE}}{VT}=\frac{V_{CC}-V_{BE}}{V_T}$$ The voltage gain is the same as CE, but opposite phase. To maintain active mode operation the voltage drop over $R_C$ must be less than $V_{CC}-V_{BE}$.
-Adding a resistor between the source and emitter ($R_S$) alters the gain. This makes the gain: $$A_v=\frac{R_C}{\frac{1}{g_m}+R_S}$$ The source resistor attenuates the signal before it reaches the amplifier, reducing the voltage gain. This is similar to CE emitter degeneration but with the phase reversed. The output impedance without the collector resistor is: $$R_{out1}=[1+g_m(R_E||r_\pi)]r_0+(R_E||r_\pi)\approx r_0+g_mr_0(R_E||r_\pi)$$ The output impedance including the collector resistor is: $$R_{out2}=R_C||R_{out1}$$ The output impedance of the CB stage is equal to $R_C$ in parallel with the impedance looking down the collector. The output impedances of the CE, CB stages are the same if both curcuits are under the same condition. This is due to the grounding of the input port when calculating the output impedance, making them the same circuit.
+Adding a resistor between the source and emitter ($R_S$) alters the gain. This makes the gain: $$A_v=\frac{R_C}{\frac{1}{g_m}+R_S}$$ The source resistor attenuates the signal before it reaches the amplifier, reducing the voltage gain. This is similar to CE emitter degeneration but with the phase reversed. The output impedance without the collector resistor is: $$R_{out1}=[1+g_m(R_E||r_\pi)]r_0+(R_E||r_\pi)\approx r_0+g_mr_0(R_E||r_\pi)$$ The output impedance including the collector resistor is: $$R_{out2}=R_C||R_{out1}$$ The output impedance of the CB stage is equal to $R_C$ in parallel with the impedance looking down the collector. The output impedances of the CE, CB stages are the same if both circuits are under the same condition. This is due to the grounding of the input port when calculating the output impedance, making them the same circuit.
 The input impedance at the emitter with CB core is: $$R_{in}\approx\frac{1}{g_m}$$ With a base resistor, this becomes: $$R_{in}\approx\frac{1}{g_m}+\frac{R_B}{\beta+1}$$ With an emitter resistor: $$R_{in}\approx\frac{1}{g_m}||R_E$$ The input impedance is generally low and can be matched to transmission line impedances of $\sim 50\Omega$.
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 ===== MOSFETs as resistors =====
-MOSFETs can be used as resistors, and are advantageous due to their small size and changable resistance. When configured with a drain and source resistor, the output gain from the drain is: $$A_v=\frac{-R_D}{\frac{1}{g_m}+R_S}$$ We can replace the source resistor with a MOSFET in a diode configuration (gate connected to drain) and the drain resistor with a secondary input. This gives the source resistance as $\frac{1}{g_{m3}}||r_{03}$ and the drain resistance as $r_{02}$. The gain then becomes: $$A_v=-\frac{r_{02}}{\frac{1}{g_{m2}+\frac{1}{g_{m3}}||r_{03}}}$$
+MOSFETs can be used as resistors, and are advantageous due to their small size and changeable resistance. When configured with a drain and source resistor, the output gain from the drain is: $$A_v=\frac{-R_D}{\frac{1}{g_m}+R_S}$$ We can replace the source resistor with a MOSFET in a diode configuration (gate connected to drain) and the drain resistor with a secondary input. This gives the source resistance as $\frac{1}{g_{m3}}||r_{03}$ and the drain resistance as $r_{02}$. The gain then becomes: $$A_v=-\frac{r_{02}}{\frac{1}{g_{m2}+\frac{1}{g_{m3}}||r_{03}}}$$
 The diode configuration connects the gate to the drain. Here the input voltage is equal to the drain-source voltage. The input current is: $$i_x=g_{m}v_1+v_1/r_0=v_x(g_m+1/r_0)$$ $$v_x/i_x=(1/g_m)||r_0$$ This is the same for both NMOS and PMOS devices. Provided $V_{GS}$ is large enough, this configuration will always be in saturation.
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 A common source stage adds a resistor to the source of the transistor. The output resistance of this configuration is: $$R_{out}=(1+g_mr_0)R_S+r_0\approx g_mr_0R_s+r_0$$ This is fairly similar to the BJT, lacking $r_{\pi}$ as the input resistance is assumed infinite in the MOSFET case. Similar to BJT, degeneration boosts the output impedance. Substituting the source resistor with a diode configured MOSFET gives: $$R_{out}=r_{01}\left(1+g_{m_1}\frac{1}{g_{m_2}||r_{02}}\right)+\frac{1}{g_{m2}}||r_{02}\approx r_{01}\left(1+g_{m1}\frac{1}{g_{m2}}\right)+\frac{1}{g_{m2}}$$ Using multiple MOSFETs as drain resistors adds the resistance in parallel. This shows the MOSFET being a versatile resistor when connected to the drain or a separate voltage source.
-For CE AND CS staging with a diode connected load, the gain for BJT is: $$A_v=-g_{m1})r_2||1/g_{m2}\approx-1$$ Where the diodes are the same as $r_2>>\frac{1}{g_{m2}}$. In MOSFETs common source, the gain is: $$A_v=-g_{m1}\frac{1}{g_{m2}}=-\sqrt{\frac{(W/L)_1}{(W/L)_2}}$$ With channel length modulation, the gain becomes: $$A_v=-g_{m1}\left(\frac{1}{g_{m2}}||r_{02}||R_{01}\right)$$
+For CE AND CS staging with a diode connected load, the gain for BJT is: $$A_v=-g_{m1}(r_2||1/g_{m2})\approx-1$$ Where the diodes are the same as $r_2>>\frac{1}{g_{m2}}$. In MOSFETs common source, the gain is: $$A_v=-g_{m1}\frac{1}{g_{m2}}=-\sqrt{\frac{(W/L)_1}{(W/L)_2}}$$ With channel length modulation, the gain becomes: $$A_v=-g_{m1}\left(\frac{1}{g_{m2}}||r_{02}||R_{01}\right)$$
 ==== Common gate ====
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 ==== Source follower ====
-The source follower is similar to the BJT emitter follower. There is a resisitor connected to the emitter, where the output is taken. The input is provided to the gate. The gain is: $$A_v=\frac{g_m(r_0||R_L)}{1+g_m(r_0||R_L)}<1$$ The input impedance is infinite and the output impedance is: $R_{out}=\frac{1}{g_m}||r_0||R_L$. The output impedance is relatively low with a high input impedance, making it a good candidate as a buffer.
+The source follower is similar to the BJT emitter follower. There is a resistor connected to the emitter, where the output is taken. The input is provided to the gate. The gain is: $$A_v=\frac{g_m(r_0||R_L)}{1+g_m(r_0||R_L)}<1$$ The input impedance is infinite and the output impedance is: $R_{out}=\frac{1}{g_m}||r_0||R_L$. The output impedance is relatively low with a high input impedance, making it a good candidate as a buffer.
 Common biasing has a resistor between $V_{DD}$ and the gate $R_G$ and capacitors between the input and output. $$I_D=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_DD-I_DR_S-V_{TH})^2$$
+====== Cascode configurations ======
+===== Cascode current sources =====
+A resistive current source has a linear relationship between current and voltage. An ideal current source has a constant relationship between current and voltage, effectively immune to resistance. For a MOSFET, the saturation region functions effectively as an ideal current source, with the current independent of the voltage provided $V_{DS}$ doesn't fall into the triode region. A NMOS draws current from a point to ground, sinking the current. A PMOS draws current from $V_{DD}$ to a point, sourcing current. In both, the rest of the circuit must be connected to the drain for the transistor to act as a current source. The same is true for BJTs. This is because we need a constant $V_{BE}$ and a large $R_{out}$. Using a transistor as a current source allows us to maximise the voltage gain, realising the same gain at a lower voltage, with a smaller voltage drop. Additionally, transistors are smaller than resistors, saving space on an IC.
+The Early effect affects the current source, by adding in a resistance, but this can be reduced by adding emitter degeneration. We can replace the emitter resistor with a cascode transistor. $$R_{out}=[1+g_m(R_E||r_\pi)]r_0+R_E||r_\pi=[1+g_{m1}(r_{02}||r_{\pi1})]r_{01}+r_{02}||r_{\pi1}\approx g_{m1}r_{01}(r_{02}||r_{\pi1})$$ Adding the emitter resistor massively increases the output impedance, but does so with diminishing terms. The maximum output impedance is: $$R_{out,max}=\beta_1r_{01}$$ The maximum output is bounded by $r_{\pi}$ from the first transistor. The first transistor is the one closest to the rest of the circuit.
+For a CMOS cascode stage, the output resistance is: $$R_{out}=(1+g_mR_s)r_0+R_S=(1+g_{m1}r_{02})r_{01}+r_{02}=r_{02}(g_{m1}r_{01}+1)\approx g_{m1}r_{01}r_{02}$$ This is the same as BJT, but with out $r_\pi$. The output impedance is proportional to the intrinsic gain of the cascode device. Unlike the BJT cascode, the output impedance is not limited by $\beta$.
+Parasitic resistance is unwanted resistance due to a manufacturing fault and inherent physical properties. It effectively adds a resistor in parallel to the faulty component.
+A false cascode is a circuit that resembles a cascode circuit, but fails to boost the output resistance. This can be done by using a pnp in place of an npn transistor.
+===== Cascode amplifiers =====
+The gain of a common emitter stage is: $$A_v=-g_m(R_D||r_0)$$ $R_D$ can be substituted for an ideal current source, making the gain dependent only on $r_0$, which we can increase with a cascode. This can be done by adding a transistor between the input transistor and the output. The output impedance is: $$R_{out}=[1+g_{m2}(r_{01}||r_{\pi2})]r_{02}+R_{01}||r_{\pi2}\approx g_{m2}r_{02}(r_{01}||r_{\pi2})$$ The gain then becomes: $$A_v=-g_{m1}g_{m2}r_{02}(r_{01}||r_{\pi2})$$ The gain is increased by increasing the output impedance. This could be thought of as a CE stage in series with a CB stage. The same can be done with MOSFETs, removing the $r_{\pi}$ terms. $$A_{v}=-G_mR_{out}\approx-g_m[)1+g_{m2}r_{02}r_{01}+r_{02}]\approx-g_{m1}r_{01}g_{m2}r_{02}$$
+We can replace the ideal current source with a transistor acting as a current source. The current source transistor needs to be of the opposite type to the amplifier, such that the collector is visible to the output. This then makes the gain: $$A_v\approx g_{m1}g_{m2}r_{02}(r_{01}||r_{\pi2})||r_{03}$$ We can increase $r_{03}$ by making it a cascode stage. The cascode then makes the whole system output impedance: $$R_{out}\approx g_{m3}r_{03}(r_{04}||r_{\pi3})||g_{m2}r_{02}(r_{01}||r_{\pi2})$$ The first term is from the current source and the second is from the amplifier. For the MOSFET version, we send $r_{\pi}\to\infty$.
+===== Short circuit transconductance =====
+The short circuit transconductance method is based on: $$A_v=-G_mR_{out}$$ To find the gain, we need the output impedance and $G_m$. We ground the output, and treat the circuit as a whole. In some cases, $G_m$ will be equal to the transconductance of an individual transistor in the circuit. $G_m$ can be found by grounding the output to the circuit and finding the current going into the output compared to the input voltage. The output resistance can be found by grounding the input and applying a small test voltage to the output.
+===== Current mirrors =====
+Despite biasing, there are many externally dependent variables, e.g. $V_t$, $V_{CC}$, etc. A band gap reference circuit creates a temperature and supply independent bias source. The stable bias produces the "golden current". The typical band gap circuit is complex and prohibits its use multiple times for a large IC. Copying the golden current without duplicating the band gap circuitry can be done with current mirrors.
+A current mirror ideally duplicates its input current. This can be done by creating a specific $V_{BE}$ and using it to create a copy of the current. The voltage can be created with a diode configured BJT, which creates the base-emitter voltage which enables the current to flow through the transistor. No current is assumed to flow into the base of the transistor. This can be directly connected to the base of another transistor. As both transistors have the same $V_{BE}$, their $I_C$ is ideally the same. $$I_{copy}=\frac{I_{S1}}{I_{S,ref}}R_{REF}$$ Provided the transistors are very similar, the copied current is similar to the reference. This can be duplicated by connecting more transistors in parallel.
+Connecting the collectors of some transistors allows us to multiply the reference current by the number of transistors. This effectively increases the area of the transistor. Taking the reference current and inputting it into multiple reference transistors allows us to fractionally scale the reference current.
+The base current results in the difference between $I_{REF}$ and $I_{copy}$. This is because $I_{REF}$ splits and only $I_{C,REF}$ is copied. Because the $I_{B,REF}$ needs to supply the base current for all the BJTs, the more copies we make, the greater the error. This doesn't exist for MOSFETS as they have no gate current. We have a current of $\frac{I_{copy}}{\beta}$ going toward the copying transistors and a current of $\frac{I_{copy}}{n\beta}$ going toward the reference transistor. From this, we can find the $I_{REF}$: $$I_{REF}=I_{C,REF}+\frac{I_{copy}}{\beta}\frac{1}{n}+\frac{I_{copy}}{\beta}$$ As $I_{copy}=nI_{C,REF}$, we can find the copied current: $$I_{copy}=\frac{n_{I_{REF}}}{1+\frac{1}{\beta}(n+1)}$$ As $n$ increases, so does the copy error. Likewise, small values of $\beta$ lead to a larger error in $I_{copy}$. For large $\beta$ and moderate $n$, $I_{copy}\approx I_{REF}$.
+We can improve the current mirror accuracy by adding a transistor between the reference and base currents, such that the emitter is connected to the base of the mirroring transistors. This further reduces the draw on the base current by a factor of $\beta$. The current into the base of this transistor becomes: $$I_{B,F}=\frac{I_{copy}}{\beta^2}\left(1+\frac{1}{n}\right)$$ The copied current then becomes: $$I_{copy}=\frac{nI_{REF}}{1+\frac{1}{\beta^2}(n+1)}$$
+A reference current cannot run to ground, due to its circuitry, so to make a PNP mirror, we must first use a NPN mirror and use the copied current for the PNP mirror. This does introduce some error, but it is small. MOS transistors can be used as current mirrors, and follow the same rules as BJTs. For MOSFETs, the width to length ratio is analogous to the area of the BJT, allowing us to alter the ratio of reference to copied currents.
+====== Differential amplifiers ======
+===== Large signal analysis =====
+Rectification is the process of converting AC to DC. This process results in an approximation of a flat line, with the variation from that line being ripple. This ripple is an AC component riding on the rectified DC. Sophisticated rectifiers can reduce ripple, but not eliminate it. When used for an amplifier, the ripple can add to the signal and produce noise after amplification.
+Taking the difference between two sources with the same ripple produces an output without ripple, removing it in the process. Using two common emitter transistors, connected to the same bias and $V_{CC}$ and taking the output as the difference between the stage with the input and the stage without, we can remove the source ripple and get the resultant gained signal. The duplicate stage without the input remains idle, wasting current. If we connect the input to both transistors we get no output as both stages provide the same amplification. If instead we apply a $180^\circ$ phase shifted input to the second stage, we get double the gain as the resultant signal. The phase shift can be achieved with a centre tap transformer and can be biased to produce the differential signals. A single ended amplifier is one that takes a single input. A differential amplifier is one that takes two inputs and compares two outputs. Connecting the emitters together and to a constant tail current source cause the transistors to operate as a differential pair.
+In a common mode differential pair where the biasing resistors are the same, the output voltage is: $$V_{X}=V_{Y}=V_{CC}-R_C\frac{I_{EE}}{2}$$ This produces a zero differential output. To avoid saturation, the collector voltages must not fall below the base voltages: $$V_{CC}-R_C\frac{I_{EE}}{2}\geq V_{CM}$$ Provided the transistors remain forward biased, the bias voltage can be changed without affecting the output.
+For a large differential input differential pair, the emitter voltage is determined by the higher biased transistor. This results in the other transistor being off and all the current flowing through the higher biased transistor. $$V_X=V_{CC}-R_CI_{EE}$$ $$V_Y=V_{CC}$$ Here $Q_1$ hogs all of the tail current, turning $Q_2$ off. As the difference between the two inputs depart from 0, the differential pair steers the tail current from one transistor to the other. The share of the currents is given by: $$I_{C1}=\frac{I_{EE}}{1+\exp{\frac{V_{in2}-V_{in1}}{V_T}}}$$ $$I_{C1}=\frac{I_{EE}}{1+\exp{\frac{V_{in1}-V_{in2}}{V_T}}}$$ As $V_{in1}-V_{in2}\to\infty$, being the first input increases above the second, all the current flows through $I_{C1}$ and non flows through $I_{C2}$. As $I_{C1}+I_{C2}=I_{EE}$, we can find: $$I_{C1}=\frac{I_{EE}\exp\frac{V_{in1}-V_{in2}}{V_T}}{1+\exp\frac{V_{in1}-V_{in2}}{V_T}}$$ We can then use this to find $V_{out1}$ and $V_{out2}$: $$V_{out1}=V_{CC}-R_{C1}I_{C1}=V_{CC}-\frac{R_{C1}I_{EE}\exp\frac{V_{in1}-V_{in2}}{V_T}}{1+\exp\frac{V_{in1}-V_{in2}}{V_T}}$$ $$V_{out2}=V_{CC}-R_C\frac{I_{EE}}{1+\exp\frac{V_{in1}-V_{in2}}{V_T}}$$ The difference between them then becomes: $$V_{out1}-V_{out2}=-R_C(I_{C1}-I_{C2})=-R_CI_{EE}\tanh\frac{V_{in1}-V_{in2}}{2V_T}$$
+The nonlinear region is where the current flows through only one transistor. The small signal region is for input differences of less than $10mV$. The linear region is where both transistors still flow some current and the input difference is less than $4V_T\approx 104mV$.
+===== Virtual ground =====
+A virtual ground is a point in a circuit where the voltage is 0. This can be between equally and oppositely biased resistors forming a DC virtual ground. If we then add opposite AC signals to each input, the virtual ground remains. If the DC biases are different but the AC signals are equal and opposite, then there is only an AC virtual ground.
+===== Small signal analysis =====
+For a differential pair where there is a sudden, small, equal and opposite change in the inputs, the currents rise and fall by the same amounts. $$I_{C1}=\frac{I_{EE}}{2}+\Delta I$$ $$I_{C2}=\frac{I_{EE}}{2}-\Delta I$$ For small changes at the inputs, the $g_m$ are the same and as the change in currents are the same, the common emitter node can be viewed as an AC ground.
+The transconductance is $\Delta I_C/\Delta V=g_m$. The differential gain becomes: $$A_v=\frac{\text{Change in Differential Output}}{\text{Change in Differential Input}}=\frac{-2g_m\Delta VR_C}{2\Delta V}=-g_mR_C$$ This gain is the same as one single-ended transistor. The two transistors must exhibit approximately equal transconductances and the same condition required for the common node to appear as a virtual ground. This grounding in the middle allows us to treat the differential pair as two CE "half circuits", with total gain equal to one half circuit's single-ended gain. For a perfectly symmetrical circuit, the early effect can be calculated for one of the halves and contributes equally to the other and thus the overall circuit. $$A_v=-g_mr_0$$
+Where there is a resistor connecting the emitters of the differential pair, the resistor can be halved and grounded when building the half-circuit. This is due to the virtual ground formed and the resistor affecting both halves. $$A_v=\frac{-R_C}{\frac{R_E}{2}+\frac{1}{g_m}}$$
+Where there is a pair of transistors with a common base connected to the collector of the differential pair, with a resistor connecting the each new emitter to the common base, a virtual ground is formed at the common base. This causes the gain to become: $$A_v=-g_{m1}(r_{01}||r_{03}||R_{1})$$ If instead the transistors are externally biased and the resistors are connected to each other, the gain stays the same.
+For a large signal input, the output can become clipped, becoming linear and flat for part of the signal as the gain cannot be applied. This is when there is no more current available to contribute to the gain. An input difference of $4V_T$ is sufficient to turn one side of the bipolar pair nearly off. This can be used to remove some noise occurring at the peaks of an input signal.
+In a MOS differential pair, there exists a finite differential input voltage to completely switch the current from one transistor to the other, whereas in a bipolar pair that voltage is infinite. For a BJT, the maximum differential input voltage is $|V_{in1}-V_{in2}|_{\max}=4V_T$ (larger than $10mV$ for small signal applications). For a MOS, the maximum differential input voltage is $|V_{in1}-V_{in2}|_\max=\sqrt{2}(V_{GS}-V_{TH})_{equil}$. In MOS, an input difference of the following is considered small. $$|V_{in1}-V_{in2}|<<\frac{4I_{SS}}{\mu_nC_{ox}\frac{W}{L}}$$
+===== Common Mode Rejection Ratio (CMRR) =====
+The common mode response for a differential pair is when the inputs are equal, and the output does not vary. This assumes perfect symmetry and ideal current sources. If the same noise is applied to the common mode, the output is isolated from the noise, with the noise going to the common emitter. The noise is absorbed by the infinite impedance current source. As no infinite impedance source exists, we can model the emitter resistor with $R_{EE}$, giving the common-mode gain as: $$A_v=-\frac{R_C}{2R_EE+\frac{1}{g_m}}$$ A change to the input CM voltage causes the currents in the transistors to change, leading to a change in $V_{out1}$ and $V_{out2}$. This passes some of the noise through to $V_{out1}$ and $V_{out2}$, however as $V_{out}$ is the difference, the noise is still cancelled. This is similar to the removal of ripple voltage. If the $R_C$ differ from each other, then the output voltages are not symmetrical, so any noise is passed through to the output.
+In an asymmetrical circuit, a fluctuation in the common mode is interpreted as a differential mode input. This is a common mode (CM) to differential mode (cm) conversion, $A_{CM-DM}$. For a MOSFET differential pair, the common mode gain is: $$A_{CM-DM}=\frac{\Delta R_D}{1/g_m+2R_{SS}}\approx\frac{\Delta R_D}{2R_{SS}}$$ Ideally, this should be 0, which is achieved when $R_{SS}\to\infty$ or $\Delta R_D\to 0$. If a finite tail impedance and asymmetry are both present, then the differential output will contain a portion of input common-mode signal.
+The Common Mode Rejection Ratio (CMRR) is the ratio of the differential mode gain to the common mode gain: $$CMRR_{DM}=\frac{A_{DM}}{A_{CM-DM}}$$ This is the ratio of wanted input signal amplification to unwanted common mode noise amplification. Ideally the CMRR is infinite.
+===== Single ended conversion =====
+Many components take two signals as input and produce only a single output. It can be useful to only have a single output. One way of converting is to take the only one of the outputs, say $V_{out2}$ and use that as the output, but this is not great, as it doesn't utilise the differential nature of the circuit and is still sensitive to noise. This also results in losing half the signal.
+Adding a current mirror in place of the collector resistors creates an active load which puts the current difference between the sides into the output line. $$I_3=I_1-I_2=\frac{I_{EE}}{2}+\Delta I-\left(\frac{I_{EE}}{2}-\Delta I\right)=2\Delta I$$ $$V_{out}=2\Delta I R_L$$ Usually a capacitor will be used to decouple the DC component from the output. Adding in the current mirror removes the symmetry, requiring small-signal analysis to find the gain The common emitter is no longer a virtual ground, but the circuit can still be viewed as a differential pair. The gain is: $$A_v=\frac{v_{out}}{v_{in1}-v_{in2}}=g_{mN}(r_{0N}||r_{0P})$$ Where $g_{mN}$ is the differential pair transistor transconductance, $r_{0N}$ is the differential pair Early resistance and $r_{0P}$ is the current mirror Early resistance.
+====== Frequency responses ======
+Generally, the gain of an amplifier is inversely related to the frequency of operation. $$Z_c=\frac{1}{2\pi fC}$$ Here, we can see that the amplifier's capacitance is limiting. The output of an amplifier has a capacitive load connecting the output to ground, which we can use to model the gain. $$A_v=-g_m\left(R_D||\frac{1}{C_Ls}\right)=\frac{-g_mR_D}{R_DC_Lj\omega+1}$$
+The transfer function is the gain of the system, being the relationship between the input and output $|V_{out}/V_{in}|$. $$H(j\omega)=A_0\frac{\left(1+\frac{j\omega}{\omega_{z1}}\right)\left(1+\frac{j\omega}{\omega_{z2}}\right)...}{\left(1+\frac{j\omega}{\omega_{p1}}\right)\left(1+\frac{j\omega}{\omega_{p2}}\right)...}$$ Where $A_0$ is the low-frequency gain, $\omega_z$ are the "zero" frequencies and $\omega_p$ are the "pole" frequencies. We can note that $H(j\omega)\to A_0$ as $s\to 0$, where $s=j\omega=j2\pi f$. We can use this to find the pole of the previous gain, $\omega=\frac{1}{R_DC_L}$, giving the absolute value of the gain as $\left|\frac{V_{out}}{V_{in}}\right|=\frac{g_mR_D}{\sqrt{2}}$. This is about $70\%$ of the low frequency gain, and occurs at the $-3dB$ frequency. We can show the gain on a Bode plot, which will be roughly flat initially and fall off at 20dB/decade after the 3dB frequency.
+===== Miller's Theorem =====
+Miller's theorem accounts for a floating capacitor connecting the drain and gate of the transistor. The theorem replaces the floating capacitor into two equivalent grounded capacitors. For the first node (gate/input), we have: $$Z_1=\frac{Z_F}{1-A_v}$$ For the second node (drain/output), we have: $$Z_2=\frac{Z_F}{1-1/A_v}$$ Where $A_v$ is the gain from the gate to drain.
+The input capacitance is: $$C_{in}=C_F(1+A_0)$$ The output capacitance is: $$C_{out}=C_F(1+1/A_0)\approx C_F$$ Where $A_0=-A_v$. Miller multiplication refers to the multiplicative increase in input capacitance.
+Miller's theorem is only true if we use $A_v$ and $Z_F$ at the same frequency of interest. The Miller approximation ignores the effect of the capacitor on the gain, effectively using the low frequency gain for everything, even the high frequency poles. This approximation is close to real results.
+===== Intrinsic capacitance =====
+In MOS transistors, there exists oxide capacitance from gate to channel, junction capacitances from source/drain to substrate, and overlap capacitance from gate to source/drain. These capacitances will start to effect the transistor at high frequency, as they will start acting like shorts. Some of the capacitances are from multiple regions around the MOSFET.
+With these capacitances, it is possible to define a quantity representing the ultimate speed of the transistor. The transit frequency $f_T$ is defined as the frequency where the current gain from input to output drops to 1. Normally, it is the capacitance between the base and emitter ($C_\pi$) that is the limiting factor in BJTs. We can find the transit frequency to be: $$2\pi f_T\approx\frac{g_m}{C_\pi}$$ For MOSFETS, we can find the transit frequency as: $$2\pi f_T\approx\frac{g_m}{C_{GS}}$$
+====== Feedback ======
+Two types of feedback exist, positive and negative.
+  * Positive feedback systems add a feedback signal to the input signal and are used in some specific devices, e.g. oscillators.
+  * Negative feedback systems involve subtracting a feedback signal from the input signal and are widely used for improving stability.
+===== Negative feedback =====
+For a system with a feed forward gain if $A_1$ and a feedback gain of $K$, the closed loop transfer function is: $$\frac{Y}{X}=\frac{A_1}{1+KA_1}$$ The negative feedback reduces the gain by a factor of $\frac{1}{1+KA_1}$.
+The feedback error $E$ is the modified signal applied to the feed forward system. $$E=X-X_F=\frac{X}{1+A_1K}$$ As $A_1K$ increases, the error between the input and feedback signal decreases, meaning the feedback signal is a good replica of the input. This condition is favourable for gain desensitisation/stability. In increasing the gain ($KA_1\to\infty$), we can find that $X\approx X_F$. We can use this to find the gain, and find that it is independent of $A_1$. This separates the closed loop gain from the open loop gain.
+The main advantage of negative feedback is gain desensitisation, which increases the stability of the system. It can also serve to modify the input and output impedances. The lower gain enforced by the feedback means the gain remains constant over a larger bandwidth. Keeping the error small helps to keep the system acting linearly.
+The loop gain is found by:
+  - Breaking the circuit at an arbitrary location and setting the input to ground
+  - Connecting a test voltage source such that there is clockwise current
+  - Finding the gain at the other node compared to the test input ($-\frac{V_N}{V_{test}}$)
+This is $KA_1$.